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EDCI 5890: Very Large Scale Integrated (VLSI) Design and Simulation
Design of MOS transistors, including short channel effects in sub-micron devices; scaling laws; design rules. Layout of NMOS and CMOS logic gates; power-delay calculations. Design of static and/or dynamic memories. Laboratory emphasizes schematic capture, simulation, timing analysis and testing; layout of custom IC's; use of VHDL.
- Credits
- 3
- Offered
- Fall 2026
- Campuses
- Storrs
- Requirements
- CSE 2300W or 2301; ECE 3201; open only to students in the School of Engineering.
Fall 2026 sections
Taught by Michele Back.
| Section | Type | Meets | Instructor | Campus | Room | Seats |
|---|---|---|---|---|---|---|
| 001 | LEC | TBA | Michele Back | Storrs | Online | 1 of 20 open |
Seats as of Nov 12, 2026. HuskyScheduler shows live seats when you search.
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